Asic Verification Engineer
ASIC Verification Engineer Work is 100% on site, in SCIF US citizenship is required for all positions A$ cents A cents ' not A' cents Active DoD Secret Clearance or higher and ability to obtain SAP (Special Access Program) Clearance Client is seeking an Advanced Verification Engineer to join our team of highly qualified, diverse individuals in Digital Technology.
Qualified applicant will become part of the Digital Technology department, which specializes in product designs for a variety of applications from undersea to outer space.
Roles and
Responsibilities:
The individual will perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog and Cadence Xcelium simulation tool.
This task includes but not limited to development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc.
This candidate will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.
Qualifications Description:
Basic
Qualifications:
A$ cents A cents ' not A' cents BachelorA$ cents A cents ' not A cents cents s degree (MasterA$ cents A cents ' not A cents cents s preferred) in Electrical Engineering or comparable engineering discipline A$ cents A cents ' not A' cents 9
years of design verification experience A$ cents A cents ' not A' cents Expertise in HDL (VHDL/Verilog) and HVL (SystemVerilog) A$ cents A cents ' not A' cents Experience with SystemVerilog Assertions (SVA) A$ cents A cents ' not A' cents Advanced knowledge of UVM and SystemVerilog A$ cents A cents ' not A' cents Experience with a coverage-driven verification methodology from planning through closure A$ cents A cents ' not A' cents Knowledge of industry standard interfaces A$ cents A cents ' not A' cents Experience with object oriented programming languages and concepts A$ cents A cents ' not A' cents Be able to work in teams and communicate clearly across various levels of engineers A$ cents A cents ' not A' cents Proficiency in scripting languages such as Tcl, Python or Perl.
Estimated Salary: $20 to $28 per hour based on qualifications.
Qualified applicant will become part of the Digital Technology department, which specializes in product designs for a variety of applications from undersea to outer space.
Roles and
Responsibilities:
The individual will perform functional verification of register transfer level (RTL) code of a complex ASIC at block level and SOC level using UVM (Universal Verification Methodology) and SystemVerilog and Cadence Xcelium simulation tool.
This task includes but not limited to development of testbench, tests, verification IP (VIP), verification models, coverage models, extensive simulation and debug, code coverage and functional coverage, generation and analysis of reports and metrics, documentation etc.
This candidate will have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the goals.
Qualifications Description:
Basic
Qualifications:
A$ cents A cents ' not A' cents BachelorA$ cents A cents ' not A cents cents s degree (MasterA$ cents A cents ' not A cents cents s preferred) in Electrical Engineering or comparable engineering discipline A$ cents A cents ' not A' cents 9
years of design verification experience A$ cents A cents ' not A' cents Expertise in HDL (VHDL/Verilog) and HVL (SystemVerilog) A$ cents A cents ' not A' cents Experience with SystemVerilog Assertions (SVA) A$ cents A cents ' not A' cents Advanced knowledge of UVM and SystemVerilog A$ cents A cents ' not A' cents Experience with a coverage-driven verification methodology from planning through closure A$ cents A cents ' not A' cents Knowledge of industry standard interfaces A$ cents A cents ' not A' cents Experience with object oriented programming languages and concepts A$ cents A cents ' not A' cents Be able to work in teams and communicate clearly across various levels of engineers A$ cents A cents ' not A' cents Proficiency in scripting languages such as Tcl, Python or Perl.
Estimated Salary: $20 to $28 per hour based on qualifications.
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